The present disclosure relates generally to fabrication of integrated circuits, semiconductor devices and other miniaturized devices, and more particularly, to fabrication of three-dimensional integrated circuits using thin die-to-wafer bonding.
Currently, wire bonding is being used to make connections between chips. The wire bonds are long connections which slow down the speed at which the devices can talk to each other. In addition, the number of connections that can be made between devices is limited because wire bonding uses bonding sites around the perimeter of the die to make the connections and there are a limited number of sites on the perimeter. The minimum size of the semiconductor devices is also limited by the use of wire bonding. By replacing wire bonding with three-dimensional device integration, a larger number of connections are possible and those connections will be shorter which will speed up the time it takes for the devices to communicate with each other.
As semiconductor device sizes have decreased, three-dimensional device integration has become a desired method for increasing the density of integrated circuits and/or semiconductor devices. Three-dimensional integration occurs when a plurality of semiconductor die are vertically stacked having electrical contacts disposed on both the active surface and back-side of the dies thereby increasing the electrical interconnections between the stacked dies. Typically, the die to die electrical connections have been wire bonds that require a long connection which slows the speed and limits the number of possible connections. Also due to the ultra thin nature of the die, they are difficult to handle and susceptible to breakage and contamination. Further, it is important to be able to identify and employ only good, non-defective die in building a stack.
The present disclosure contemplates a new and improved method for fabrication of three-dimensional integrated circuits using thin die-to-wafer bonding that overcomes current limitations.